Using FPGAs for Real-Time Disparity Map Calculation

Real-time stereo image matching is an important computer vision task. This paper presents the architecture and implementation of an FPGA-based stereo image processor, that produces 25 dense depth maps per second from pairs of 8-bit-perpixel gray-scale images. The system implements a modification of a previously-reported variable-window-size method to determine the best correspondence for each image pixel. The degree of parallelism of the implementation can be adapted to the available resources: increased parallelism enables the processing of larger images (at the same frame rate). The proposed architecture exploits the memory resources available in modern platform FPGAs. Two prototype implementations have been produced and validated: the smaller one can handle pairs of images of size 208 × 480 , while the larger one works for images of size 640 × 480 (both operate at 100 MHz). These results improve on previously-reported ASIC and FPGA-based designs.